About Xtacking

XtackingTM enables DRAM-like high I/O speed

With XtackingTM, the periphery circuits which handle data I/O as well as memory cell operations are processed on a separate wafer using the logic technology node that enables the desired I/O speed and functions. Once the processing of the array wafer is completed, the two wafers are connected electrically through millions of metal VIAs (Vertical Interconnect Accesses) that are formed simultaneously across the whole wafer in one process step, using the innovative XtackingTM technology, with limited increase in total cost.

XtackingTM enables higher array efficiency

In the conventional 3D NAND architecture, the periphery circuits take up ~20-30% of the die area, lowering NAND bit density. As 3D NAND technology continues to progress to 128 layers and above, the periphery circuits will likely take up more than 50% of the total die area. With XtackingTM, the periphery circuits are now above the array chip, enabling much higher NAND bit density than conventional 3D NAND.

XtackingTM: Modular approach to accelerate process development and shorten manufacturing cycle time

XtackingTMtechnology utilizes fully independent processing of the array and periphery, which offers a modularized, parallel approach to product development and manufacturing, reducing product development time by at least three months and shortening manufacturing cycle time by 20%, significantly accelerating 3D NAND time-to-market. This modular approach also opens possibilities for customized NAND flash solutions by the incorporation of innovative functionalities in the periphery.